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Ericsson

Master Thesis: Implementing a Python-Based Verification Framework for Ethernet

Ericsson Lund, Skåne County, Sweden

Telecommunications · 10,001+ employees

Yesterday
python Junior (0-2 yrs) Full-time Sweden
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About the role

Develop a Cocotb-based verification environment for Ethernet transmitter and receiver RTL designs. Implement protocol-aware scoreboards, reference models, and checkers to perform automated end-to-end verification.

What they look for

Python Cocotb Ethernet RTL SystemVerilog Verilog VHDL UVM Digital Design ASIC Verification TCL Communication Protocols Packet Generation Reference Models Problem-solving

Requirements

Currently pursuing a master’s degree in electrical engineering, computer engineering, or a related field. Requires background in digital design, RTL coding, and basic scripting experience in Python.

Full description

Join our Team

About this opportunity

Join Ericsson in Lund for a Master’s thesis focused on developing a Python-based verification framework for Ethernet transmitter and receiver designs.

Ethernet is a core communication technology in modern digital systems and robust verification is essential for validating packet generation, transmission, reception and protocol compliance. In this thesis, you will investigate how Cocotb and Python can complement traditional SystemVerilog/UVM-based verification by enabling reusable, maintainable and productive verification environments.

What you will do

  • Develop a Cocotb-based verification environment for Ethernet transmitter and receiver RTL designs.
  • Create Python-based Ethernet packet generators.
  • Drive packets into the transmitter and verify their correct reception at the receiver.
  • Implement protocol-aware scoreboards, reference models and checkers.
  • Perform automated end-to-end verification of Ethernet packet transfer.
  • Evaluate Cocotb’s effectiveness compared with traditional verification methodologies, with focus on productivity, maintainability and reusability.
  • Document the design, implementation, test strategy, results and recommendations for adoption in ASIC verification environments.

The skills you bring

  • Currently pursuing a master’s degree in electrical engineering, Computer Engineering, Embedded Systems or a related field.
  • Background in digital design and RTL coding using VHDL, Verilog, or SystemVerilog.
  • Basic scripting experience in Python and TCL; experience with Cocotb is an advantage.
  • Interest in Ethernet, communication protocols, ASIC development and digital verification.
  • Strong analytical and problem-solving skills.
  • Ability to document technical work clearly and communicate findings effectively.

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