Manager, Project Management - Chip Design

NVIDIA Tel Aviv, Tel-Aviv District, Israel

Computer Hardware Manufacturing · 10,001+ employees

7 h ago

Principal (10+ yrs) Full-time Israel

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About the role

Manage the end-to-end pre-silicon development of advanced switch ASICs from concept through tape-out. Drive post-silicon execution including chip power-on, bring-up, and qualification for production release.

What they look for

ASIC Development Project Management RTL Design Verilog UVM SystemVerilog System-On-Chip Design Design Automation Physical Design Synthesis Verification Leadership Problem-solving Communication Teamwork

Requirements

Requires a BS or MS in Computer or Electrical Engineering with at least 10 years of experience in chip design. Candidates must have 5+ years of management experience leading large engineering organizations.

Full description

NVIDIA's Switch ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development of NVIDIA's most advanced and complex switch ASICs — from concept to tape-out — and drive the chip through power-on and qualification to production release. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams.

What you'll be doing:

Development Management: Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out.
Post-Silicon Execution: Drive chip power-on, bring-up, and qualification to production release.
Execution Plans: Define and implement execution plans in collaboration with cross-discipline leaders in unit-level, full-chip, physical design, and firmware/software emulation.
Roadmap Definition: Contribute to the definition of NVIDIA's switch ASIC roadmap.

What we need to see:

BS or MS in Computer or Electrical Engineering, or equivalent experience.
10+ overall years of experience in chip design.
5+ years of chip design/verification management experience as a second- or third-level manager, leading organizations of 50+ engineers.
Proficiency in RTL design (Verilog), verification (UVM, SystemVerilog), System-On-Chip design/integration flow, and design automation.
Strong system view with the ability to collaborate across multiple interfaces.
Strong analytical and problem-solving skills.
Excellent communication and teamwork abilities.
Experience in synthesis and physical design is a plus.